The present invention generally relates to a level shifter for translating logic levels, and more particularly relates to a level shifter that can substantially eliminate a short-circuit current, which usually flows when a signal changes its logic levels.
A latch-type level shifter is one of known level shifters. FIG. 32 illustrates a specific configuration for a level shifter of this type. As shown in FIG. 32, the level shifter includes two n-channel transistors 51 and 52, two cross-coupled p-channel transistors 53 and 54 and first and second inverters 55 and 56. Each of the p-channel transistors 53 or 54 has its gate connected to the drain of the other p-channel transistor 54 or 53. The first inverter 55 inverts the level of an input signal received at an input terminal IN and is powered by a voltage supply VDD supplying a relatively low voltage of 1.5 V, for example. All the components of the level shifter but the first inverter 55 are powered by another voltage supply VDD3 supplying a relatively high voltage of 3.3 V, for example. The n-channel transistors 51 and 52 are both grounded and receive signals with mutually complementary levels, i.e., the input signal at the input terminal IN and the output signal of the first inverter 55, i.e., the inverted version of the input signal, respectively. The p-channel transistors 53 and 54 have their sources connected to the high voltage supply VDD3 and their drains connected to the drains of the n-channel transistors 51 and 52, respectively. The second inverter 56 is connected to a second node W2 at which the n- and the p-channel transistors 52 and 54 are connected together. And the output of the second inverter 56 is connected to an output terminal OUT.
Hereinafter, it will be described how this level shifter operates. Suppose, in a static state, the input signal is at logical 1 level (i.e., equivalent to the level of the supply voltage VDD) and the inverted version thereof is at logical 0 level (i.e., equivalent to the level of the ground potential VSS, or 0 V). In the following description, the logical 1 and 0 levels will be called H- and L-levels, respectively. In such a state, the n- and p-channel transistors 51 and 54 are ON, while the n- and p-channel transistors 52 and 53 are OFF. Also, in this state, a first node W1, at which the n- and p-channel transistors 51 and 53 are connected together, is at the L-(VSS) level. On the other hand, the second node W2, at which the n- and p-channel transistors 52 and 54 are connected together, is at the H-(VDD3) level. Each pair of transistors 51 and 53 or 52 and 54 meets a complementary relationship. Accordingly, no current flows in this static state.
Thereafter, when the level shifter enters an operating state with the transition of the input signal to the L-(VSS) level, the n-channel transistors 51 and 52 turn OFF and ON, respectively, as shown in FIG. 33. As a result, a short-circuit current I flows from the high voltage supply VDD3 through the p- and n-channel transistors 54 and 52 in the ON state, and the potential level at the second node W2 starts to fall from the H-(VDD3) level. And when the potential level at the second node W2 becomes lower than the threshold voltage Vtp of the p-channel transistor 53, the p-channel transistor 53 turns ON. As a result, the potential level at the first node W1 rises, the drain current of the p-channel transistor 54 decreases and the potential level at the second node W2 further falls.
Finally, the potential levels at the first and second nodes W1 and W2 reach the H- and L-levels (i.e., VDD3 level and 0 V), respectively. Then, no short-circuit current flows anymore and the second inverter 56 inverts the output logic level. As a result, the level shifter enters a standby state, or prepares for the next level transition of the input signal. In the foregoing example, the input signal changes from the H- into the L-level. However, a similar statement is applicable to the opposite situation, i.e., where the input signal changes from the L- into the H-level.
In the known level shifter, however, the potential level at the second node W2 is changed by allowing the short-circuit current to flow through the p- and n-channel transistors 54 and 52 during its operation. Thus, the level shifter dissipates a greater power disadvantageously.
In view of this drawback, a level shifter for selectively interrupting the short-circuit current in accordance with the potential level transition at the output node W2 was proposed in Japanese Laid-Open Publication Nos. 10-190438 and 7-106946, for example. FIG. 34 illustrates a configuration for the level shifter of that type. As shown in FIG. 34, the level shifter includes not only all the components of the level shifter shown in FIG. 32 but also p-channel transistors 57 and 58 as current interrupting transistors, which are disposed between the high voltage supply VDD3 and the p-channel transistors 53 and 54, respectively. The level shifter further includes inverters 59, 60, 61 and 62 as delay devices and a latch 63 of a small size. A potential at the first node W1 is applied to the gate of one current interrupting transistor 57 by way of the inverters 59 and 60. A potential at the second node W2 is applied to the gate of the other current interrupting transistor 58 by way of the inverters 61 and 62. The latch 63 is connected between the first and second nodes W1 and W2 and includes two p-channel transistors 64 and 65. These transistors 64 and 65 have their sources connected to the high voltage supply and their drains connected to the first and second nodes W1 and W2, respectively. Also, each of these transistors 64 or 65 has its drain connected to the gate of the other transistor 65 or 64.
In this level shifter with the capability of interrupting the short-circuit current, while the input signal is at the H-level, for example, the potential level at the second node W2 is also at the H-(VDD3) level. In such a state, the current interrupting transistor 58 is OFF and the high voltage supply VDD3 is disconnected from the p-channel transistor 54. On the other hand, the potential level at the first node W1 is at the L-level (i.e., 0 V). In such a state, the p-channel transistor 53 and current interrupting transistor 57 are ON and the high voltage supply VDD3 is connected to the p-channel transistor 53.
When the input signal changes into the L-level, the level shifter enters an operating state. In that state, the n-channel transistor 51 turns OFF to disconnect the first node W1 from the ground. On the other hand, the n-channel transistor 52 turns ON to ground the second node W2. As a result, the potential level at the second node W2 falls. This potential drop is transmitted to the p-channel transistor 58 but its arrival is delayed for a predetermined amount of time by the two delay devices 61 and 62. During this delay, the potential drop at the second node W2 turns the p-channel transistor 53 ON to connect the high voltage supply VDD3 to the first node W1. As a result, the potential level at the first node W1 rises and the p-channel transistor 54 turns OFF. Thereafter, the current interrupting transistor 58 turns ON. Accordingly, even if the n-channel transistor 52 turns ON during this operation, no short-circuit current flows from the high voltage supply VDD3 through the p- and n-channel transistors 54 and 52. As a result, the power dissipation can be cut down. However, if the potential rise at the first node W1 turns the current interrupting transistor 57 OFF after the predetermined time delay, then the first node W1 might enter a high impedance state and the output might be indefinite. To avoid such an unwanted situation, the latch 63 turns its internal p-channel transistor 64 ON responsive to the potential drop at the second node W2. In this manner, the high voltage supply VDD3 is connected to the first node W1, thereby pulling up the first node W1.
In the level shifter with the short-circuit current interrupting capability, each of the p-channel transistors 64 and 65 in the latch 63 should have its gate length L and ON-state resistance both increased sufficiently so as to be operable even at a low voltage. However, the n-channel transistors 51 and 52 usually have a small operating current. Accordingly, the capacitance to be driven by these n-channel transistors 51 and 52 increases in that case. As a result, a long time delay is caused after the input signal has changed its logic level and before the logic level at the output terminal OUT of the level shifter changes.
Also, in the level shifter with the short-circuit current interrupting capability, the latch 63 is connected to the drains of the n-channel transistors 51 and 52. Accordingly, to change the logic level at the output terminal OUT, the drain potentials of these n-channel transistors 51 and 52 (i.e., the potentials at the nodes W1 and W2) should be changed all the way from the high supply voltage VDD3 into the ground potential VSS or vice versa. And this is another factor increasing the delay. Nevertheless, if the current-carrying capacity of the n-channel transistors 51 and 52 is increased to shorten the delay, then these n-channel transistors 51 and 52 should have their size increased. Particularly when the low supply voltage VDD is decreased, the current, flowing through these n-channel transistors 51 and 52, further decreases, and the size of these transistors 51 and 52 should be further increased. As a result, these transistors 51 and 52 will occupy even larger areas on the chip.
It is therefore an object of the present invention to provide a level shifter with the short-circuit current interrupting capability that can operate at high speeds, or at a minimum delay, without using the latch of a small size.
To achieve this object, a level shifter according to the present invention includes a resistor connected to respective nodes, at which current interrupting transistors and cross-coupled transistors are connected together, thereby pulling those nodes up to a high voltage using this resistor.
As an alternative means for accomplishing this object, another level shifter according to the present invention has no pair of cross-coupled transistors.
A level shifter according to the present invention includes first and second n-channel transistors, first and second cross-coupled p-channel transistors, current interrupting section and at least one resistor. Each of the n- and p-channel transistors includes first, second and control terminals. The first and second n-channel transistors receive an input signal and its complementary signal at their respective control terminals and are powered by a first voltage supply. The first terminals of the first and second n-channel transistors are grounded, while the second terminals thereof are connected to first and second nodes, respectively. The first terminals of the first and second p-channel transistors are connected to a second voltage supply, while the second terminals thereof are connected to the first and second nodes, respectively. The current interrupting section interrupts a short-circuit current by disconnecting the first or second p-channel transistor from the second voltage supply when the input signal changes its level. And the resistor connects the second voltage supply to the first or second node while the input signal is in a steady state.
In one embodiment of the present invention, the resistor preferably has a high resistance value so that a current, flowing from the second voltage supply through the resistor itself, has a value almost equal to zero.
In another embodiment of the present invention, the level shifter preferably further includes a next-stage inverter connected to the second node. And gate capacitances of the next-stage inverter and the first p-channel transistor are preferably set so small as to allow the potential level at the second node to fall quickly.
In still another embodiment, the second and fourth p-channel transistors preferably have such a size as allowing the potential level at the second node to rise quickly.
In the inventive level shifter, even if both terminals of the first or second node are disconnected in a steady state in which the input signal has a constant level, the first or second node is connected to the second voltage supply via the resistor and pulled up. Thus, the level shifter of the present invention needs no small-sized latch for the pull-up purposes. That is to say, the capacitance to be driven by the first and second n-channel transistors, which should change the logic levels of the pair of cross-coupled p-channel transistors (i.e., a latch), can be reduced. Accordingly, when the input signal changes its level, the potential level at the first or second node falls more quickly, or the delay shortens. As a result, the level shifter can operate at higher speeds. In addition, although the level shifter of the present invention needs the resistor for pull-up purposes, the resistor is much smaller in size than the latch of the small size. Thus, the area occupied by the resistor on the chip is much smaller than that occupied by the small-sized latch.
Particularly, the potential level can fall even more quickly at the second node. Accordingly, the delay can be further shortened and the level shifter can operate at even higher speeds.
Another level shifter according to the present invention includes first and second transistors, pre-charge circuit, level detector and pre-charge controller. Each of the first and second transistors includes first, second and control terminals. The first and second transistors receive an input signal and its complementary signal at their respective control terminals and are powered by a first voltage supply. The first terminals of the first and second transistors are grounded, while the second terminals thereof are connected to first and second nodes, respectively. The pre-charge circuit pre-charges the first and second nodes to a voltage level of a second voltage supply. The level detector detects a potential drop at the first and second nodes. And the pre-charge controller controls the pre-charge circuit.
In one embodiment of the present invention, capacitances of gates connected to the first and second nodes are set so small in the level detector as to allow the potential level at the first and second nodes to fall quickly.
The inventive level shifter includes a level detector with a high switching level for detecting a potential drop at the first or second node. Accordingly, when the potential level at the first or second node decreases to less than the switching level of the level detector, the detector detects the potential level to change the output logic levels. Thus, compared to the known level shifter in which the output logic level does not change until the potential level at the first or second node is pulled all the way up to a high voltage, the inventive level shifter can operate much faster with its power dissipation reduced considerably.
In addition, according to the present invention, the potential level can fall at the first or second node quickly enough because a smaller current flows from its associated gate into the first or second node. Thus, the delay can be shortened and the level shifter can operate much faster.